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You searched for: mediatype:texts AND collection:theides AND subject:"Line Edge Roughness (LER)"
[texts]Design and Analysis of Power and Variability Aware Digital Summing Circuit - Aminul Islam, Mohd. Hasan
Due to aggressive scaling and process imperfection in sub-45 nm technology node Vt (threshold voltage) shift is more pronounced causing large variations in circuit response. Therefore, this paper presents the analyses of various popular 1-bit digital summing circuits in light of PVT (process, voltage and temperature) variations to verify their functionality and robustness. The investigation is carried with ±3ó process parameters and ±10% VDD (supply voltage) variation by applying Gaussian dis...
Keywords: Carbon nanotube field effect transistor (CNFET); transmission gate (TG); random dopant fluctuation (RDF); line edge roughness (LER); energy delay product (EDP)
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